1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor array substrate and a method for manufacturing the same, which has a “U”-shaped common line formed in a pixel region in order to improve an aperture ratio, and can decrease a resistance by increasing a line width of the common line from a region near a thin film transistor to a region below a drain electrode and can prevent defects such as line cut, etc.
2. Discussion of the Related Art
With the progress of an information-dependent society, the demand for various display devices has increased. To meet such a demand, efforts have recently been made to research flat panel display devices such as liquid crystal display (LCD) devices, plasma display panels (PDPs), electro luminescent display (ELD) devices, vacuum fluorescent display (VFD) devices, and the like. Some types of such flat panel display devices are being practically applied to various appliances for display purposes.
In particular, LCDs have been used as a substitute for cathode ray tubes (CRTs) in association with mobile image display devices because LCDs have advantages of superior picture quality, low weight, thinness, and low power consumption. Thus, LCDs are currently most widely used. Various applications of LCDs are being developed in association with not only mobile image display devices such as monitors of laptop computers, but also monitors of TVs to receive and display broadcasting signals, and monitors of computers.
Successful application of such LCDs to diverse image display devices depends on whether or not the LCDs can realize desired high picture quality including high resolution, high brightness, large display area, and the like, while maintaining desired characteristics of low weight, thinness, and low power consumption.
Hereinafter, a conventional thin film transistor array substrate will be described with reference to the annexed drawings.
FIG. 1 is a plan view illustrating one pixel of a conventional thin film transistor array substrate, and FIG. 2 is a sectional view taken along line I-I′ of FIG. 1.
A conventional thin film transistor array substrate includes a first substrate 10 and a second substrate (not shown) which are attached to each other with a predetermined space therebetween, and a liquid crystal layer (not shown) interposed between the first substrate 10 and the second substrate.
Describing in more detail, as shown in FIGS. 1 and 2, the conventional thin film transistor array substrate includes crossing gate lines 11 and data lines 12 on the first substrate 10. The crossing gate lines 11 and data lines 12 define pixel regions. A thin film transistor (TFT) is formed at each intersection of the gate lines 11 and the data lines 12. A pixel electrode 13 is formed in each pixel region.
The thin film transistor (TFT) includes a gate electrode 11a that is formed to be protruded from the gate line 11, a source electrode 12a that is formed to be protruded from the data line 12 and overlaps the gate electrode 11a, and a drain electrode 12b that is spaced apart from the source electrode 12a on the gate electrode 11a. An island-shaped semiconductor layer 14 is formed to cover the gate electrode 11a while being in contact with lower surfaces of the source electrode 12a and the drain electrode 12b. The semiconductor layer 14 has a laminated structure including a lower amorphous silicon layer 14a and an upper impurity layer (n+ layer) 14b disposed on the amorphous silicon layer 14a. 
A gate insulating film 15 is interposed between the semiconductor layer 14 and the layer including the gate line 11, the gate electrode 11a and a common line 21. A protective film 16 is interposed between the pixel electrode 13 and the layer including the data line 12 and the source/drain electrodes 12a and 12b. Therefore, insulation between the electrodes can be kept.
The common line 21 is formed across the pixel region and parallel to the gate line 11. A storage capacitor is defined at a region in which the common line 21 and the pixel electrode 13 overlap each other. The storage capacitor includes electrodes defined by the common line 21 and the pixel electrode 13, and dielectric layers defined by the gate insulating film 15 and the protective film 16 that are interposed between the common line 21 and the pixel electrode 13.
However, in such a case, because the storage capacitor is defined at the region in which the common line 21 and the pixel electrode 13 overlap each other, loss of an aperture ratio is generated by as much as the overlap area of the common line 21 and the pixel electrode 13 by the arrangement of the common line 21 which is generally made of light shielding metal.
Although not illustrated, the second substrate includes a black matrix layer (not shown) for blocking incidence of light to a region other than the pixel regions. The second substrate also includes R, G and B color filter layers (not shown) formed at a region corresponding to each pixel region and adapted to reproduce color tones, and a common electrode (not shown) formed on the color filter layers and adapted to reproduce an image.
The conventional thin film transistor array substrate as constituted above has the following problems.
When the common line composing the storage capacitor is formed to overlap the pixel electrode, loss of an aperture ratio is generated by as much as the overlap area of the common line and the pixel electrode.
If a line width of the common line is reduced or a shape of the common line is changed in order to prevent the loss of an aperture ratio, the line may be cut, or resistance of the common line may become large, which causes shutdown crosstalk. Thus, it is also required to improve such a problem.